A CMOS microprocessor comprises dynamic and static logic circuits including a plurality of CMOS transistors. Each transistor is formed by photolithographic techniques and is comprised of a plurality of layers of semiconductor material in a field effect transistor (FET) configuration. The FET's are interconnected by polysilicon and metallic patterns as is well known.
Such a FET has a characteristic threshold and, ofter, noise causes voltage excursions on the polysilicon and metallic lines which exceed that threshold and cause unwanted switching of the FET to occur. For example, it is common for the FET's in a microprocessor to be organized into a programmable logic array (PLA), having Decoder and ROM portions, with associated ground and power BUSES. The stored charges in such FET's often produce voltages which are operative to discharge similar FET's, associated with the ground and power BUSES by exceeding the voltage thresholds at which such associated FET's respond. A consequence of such unwanted switching is reduced operating margins and lower chip yield as is well understood.